1. Field of the Invention
The present invention relates to a TAD (time analog/digital) type analog-to-digital (A/D) converter which converts a voltage level of an analog input signal into one numeral value by using only digital circuits.
2. Description of Related Art
A TAD type A/D converter having only digital circuits has been proposed. For example, Published Japanese Patent First Publication No. H05-259907 discloses an A/D converter wherein a voltage level of an analog input signal is converted into numerical digital data. This converter has a pulse delay circuit with a plurality of delay units. The delay units simultaneously receive the analog input signal, so that the delay units have the same delay time depending on the voltage level of the analog input signal. That is, the delay time is changed with the voltage level. A pulse signal passes through a signal line connecting the delay units in series while being delayed in each delay unit by the delay time, and the number of delay units through which the pulse signal passes within a predetermined measuring time is calculated from the position of the pulse signal in the pulse delay circuit. The converter outputs numerical digital data corresponding to the calculated number of delay units as A/D converted data.
Further, a TAD type A/D converter outputting A/D converted data at high resolution has been required to convert a voltage level of an analog input signal into digital data with high precision. For example, Published Japanese Patent First Publication No. 2004-7385 discloses an A/D converter wherein a voltage level of an analog input signal is converted into numerical digital data at a resolution higher than that corresponding to the delay time of one delay unit, without shortening the delay time. That is, the resolution error in the digital data is set to be smaller than the change of the voltage level in one delay time.
A schematic block diagram of the A/D converter disclosed in the Publication No. 2004-7385 is shown FIG. 1. As shown in FIG. 1, an A/D converter 101 has a pulse delay circuit 102 with M (M is an integer equal to or larger than 2) delay units, N (N is an integer equal to or larger than 2) coding circuits 103, N latch circuits 109, and an adding circuit 110. The delay units of the delay circuit 102 simultaneously receive an analog input signal. A pulse signal passes through a series of delay units while being delayed in each delay unit by a delay time Td. The delay units have the same delay time, and the delay time Td corresponds to the voltage level of the analog input signal. The pulse signal outputted from the i-th (i=1, 2, - - - , M) delay unit is delayed by the delay time Td from the pulse signal outputted from the (i−1)-th delay unit.
N sampling clocks CK1, CK2, - - - , CKN are inputted to the N coding circuits 103, respectively. Each sampling clock has a pulse every sampling period Ts. The phase of the sampling clock CKj (j=1, 2, - - - , N) is shifted by a shift time Td/N from the phase of the sampling clock CKj−1. The j-th coding circuit 103 latches the pulse signal PA delayed in each delay unit in synchronization with the leading or trailing edge of the clock CKj every sampling period Ts and converts M latched values of the signal PA into numeral data DTj composed of the M values arranged in series.
A system clock CKS is inputted to the coding circuits 103, the latch circuits 109 and the adding circuit 110. The system clock CKS has a pulse every sampling period Ts. In synchronization with each leading or trailing edge of the system clock CKS, the j-th coding circuit 103 outputs the numeral data DTj, and the j-th latch circuit 109 latches the numeral data DTj and outputs the numeral data DTj to the adding circuit 110. The adding circuit 110 calculates the sum of the numeral data DT1 to DTN as A/D converted data DT. The data DT corresponds to the voltage level of the analog input signal.
A schematic block diagram of the adding circuit 110 is shown in FIG. 2. As shown in FIG. 2, the adding circuit 110 has a binary tree structure classified into P stages (P=[log2N]; [X] indicates a value obtained by raising a fraction Fx of the value X, [X]=X+1−Fx when Fx>0, [X]=X when Fx=0). In this prior art, N=2P is satisfied. On the k-th stage (k=1, 2, - - - , P), there are N/2k (=2P−k) adder units. The units are hierarchally connected with one another. Each adder unit of the k-th stage has an adder ADD and a latch circuit LT. The adder ADD of the k-th stage calculates a sum of two pieces of numeral data received from the (k−1)-stage, and the latch circuit LT latches the sum in response to the system clock CKS and outputs the sum to one adder ADD of the (k+1)-th stage as numeral data. Therefore, the A/D converted data DT is finally outputted from the latch circuit LT of the P-th stage.
Therefore, as compared with a case where A/D converted data is obtained only from the numeral data DT1 in the same manner as in the A/D converter disclosed in Publication No. H05-259907, the A/D converter 101 can convert the voltage level of the analog input signal into the digital data at a higher resolution (i.e., with higher precision). The converter 101 can convert the voltage level of an analog signal into digital data with higher precision as the number N of the coding circuits 103 is increased.
However, the latch circuits 109 of all stages latch numeral data in response to the same system clock CKS. Therefore, it takes one sampling period Ts in each stage to calculate the sum of the numeral data. FIG. 3 is a timing chart of adding calculations performed in the adding circuit 110 in case of N=4 and P=2. As shown in FIG. 3, in the adding circuit 110, it takes P sampling periods P×Ts to obtain the A/D converted data DT from the N digital data DT1 to DTN. Therefore, when the number N of the coding circuits 103 is increased to heighten the precision of the calculation performed in the converter 101, the period of time required for the calculation in the adding circuit 110 is increased. That is, the period of time required to obtain the A/D converted data DT is undesirably increased.
To precisely perform a servo control in a vehicle at high speed, application programs requiring the feed-back of A/D converted data at high speed are used. However, because a conventional A/D converter needs a long time to obtain A/D converted data from an analog signal, the conventional A/D converter cannot be used to execute the application programs. Therefore, an A/D converter calculating digital data at high speed with high precision is required.